Switching power converters such as flyback converters or buck converters require a careful sequence of events at startup to ensure reliable and safe operation of both the switching power converter and any devices receiving power from the switching power converter. It is thus conventional for a switching power converter to include a power-on-reset (POR) circuit to manage the startup process. An example switching power converter 100 including a POR circuit 105 is shown in FIG. 1. An input voltage V_IN such as the rectified input voltage from an AC mains drives a power supply capacitor C1 through a startup resistor R1 to produce the power supply voltage V_CC. POR circuit 105 monitors the V_CC voltage to determine whether the V_CC power supply voltage is sufficiently high before initiating startup of a power stage 110 in switching power converter 100 through the assertion of a POR output signal (POR_OUT). A controller 115 responds to the assertion of the POR output signal by initiating the cycling of a power switch within power stage 110 to drive an output voltage V_OUT. During the cycling of the power switch, another path (for example, the auxiliary winding in a flyback converter embodiment) supports the V_CC power supply voltage.
But the cycling of the power switch cannot occur until POR circuit 105 asserts the POR output signal. While POR circuit 105 monitors the power supply voltage V_CC prior to asserting the POR output signal, it draws a POR current (I_POR) that is discharged to ground. The amount of the POR current has a direct impact on the delay necessary during startup until the power supply voltage V_CC reaches the POR threshold. The discharge of the POR current by POR circuit 105 is shown in further detail in FIG. 2. The startup resistor R1 and power supply capacitor C1 are as discussed with regard to FIG. 1. POR circuit 105 samples the power supply voltage V_CC through a voltage divider formed by a serial combination of a resistor R2 and a resistor R3 to produce a divided version of V_CC across resistor R3. A serial combination of a resistor R4 and a zener diode D1 produces a reference voltage across the zener diode D1 that a comparator U1 compares to the divided version of V_CC. In response to the divided version of V_CC exceeding the reference voltage, comparator U1 asserts the POR output signal (POR_OUT). Although such POR operation is conventional, the voltage divider will discharge the POR current (I_POR) into ground.
The load from the POR current may be better appreciated with reference to FIG. 3, which illustrates the V_CC waveform during startup. Upon application of the input voltage, V_CC begins to ramp up at a slope that depends primarily on the resistance for R1, the capacitance for C1, and the amplitude of the POR current. As the POR current is increased, the slope for the ramping of V_CC is decreased, which lengthens the delay necessary before V_CC crosses the POR threshold. At that point, V_CC drops due to the power consumption by control functions initiated by the assertion of the POR output signal. V_CC will then stabilize as the power switch cycles and drives the output voltage.
With regard to this POR process, note that it is conventional to have to design a switching power converter so as to satisfy a startup timing requirement at which the output voltage is regulated within a required output voltage tolerance (the minimum V_OUT regulation time). Achieving such a timing requirement is of course affected by the delay from the POR process. It is thus desirable to shorten the time needed for V_CC to cross the POR threshold. However, achieving such a reduction in the POR process delay faces several hurdles. For example, the minimum V_OUT regulation time must be satisfied even when the input voltage is at some minimum required value. To speed up the POR process despite such a relatively low value of the input voltage can be achieved by reducing the resistance of the startup resistor R1. But such a resistance reduction then increases power dissipation, which lowers operating efficiency and system reliability. To provide the low resistance while maintaining efficiency, it is conventional to decouple the start-up resistor after the POR process completion such as by isolating it through a switched-off depletion mode field effect transistor (FET). But this increases cost and complexity. Alternatively, the capacitance of the power supply capacitor C1 may be reduced but this capacitance has be sufficient to power the internal control circuitry during startup such that the capacitance has a well-defined minimum value.
Accordingly, there is a need in the art for a switching power converter power-on-reset circuit with reduced power consumption and increased operating speed.